Modern integrated circuits may have millions of transistors or “gates” created on monolithic substrates of silicon. These circuits, perhaps two tenths of an inch square, are quite complex in their internal organization. This complexity makes it difficult to test whether they are functioning properly in accordance with their design, and also whether the design itself was without errors. Early testing of the design on integrated circuit simulators is quite important, since the cost of having to correct a flawed design after the integrated circuit is already being manufactured can be extremely high.
For this reason, integrated circuit designs are put through a rigorous design testing process before the circuits are manufactured. This process is called “design verification” and it is performed in software or hardware simulators that are configured to imitate the operation of the integrated circuit.
Each succeeding generation of integrated circuits poses new design verification problems. Following Moore's law, design complexity is doubling every 12-18 months, which causes design verification complexity to increase at an exponential rate. In addition, competitive pressures increasingly demand shorter time to market. The combination of these forces has caused an ever worsening “verification crisis”.
Simulation-based functional verification is a popular method of functional verification, and is widely used within the digital design industry as a method for finding defects within designs. A variety of products are available in the market to support simulation-based verification methodologies. However, a fundamental problem with conventional simulation-based verification approaches is that they are slow and often do not uncover all design errors due to the unavoidable shallowness of the tests and the limited time available to run simulations.
One way for testing a design is with the use of testbench modules that are designed into the design under test using a hardware description language (HDL), for example. The testbench modules drive the input ports of the hardware and check output values. However, since the testbench modules are hardcoded into the design, changing the testbench would require rebuilding the entire design under test. For a large design, the time required may be considerable.
Another way to test a design is to create waveforms (a timed list of input signals to the design) and drive these input signals during simulation at the appropriate times. The waveforms may be changed without rebuilding the design. However, comparing actual output to expected output using waveforms may be difficult because the output signals may have to be precisely timed, which may be difficult during simulation.
A method and system that address these and other related issues are therefore desirable.